Tiva-C Launchpad GPIO output – Blinky LED
GPIO is the most basic form of input output interface that enables a processor to interact with outside world! The Tiva-C TM4C123GXL Launchpad (TM4C123GH6PM MCU) contains of 43 GPIOs categorized in various ports i.e GPIOx where x = A-F, K-N, P-Q. Not all these ports are available on the Launchpad.
The following shows various GPIOs Ports/Pins available on TM4C123GXL Launchpad.
In this tutorial we will blink on board Red LED. From board reference manual, Red LED is connected to PF.1 pin as shown in the Figure-2. In order to blink the LED, the respective GPIO pin (PF.0 in this case) needs to be configured as a Digital Output.
Following are the steps to configure a GPIO Pin as a Digital Output in general and PF.1 in specific on TM4C123GXL Launchpad.
1. GPIOx Port Bus Selection:
Each GPIO Module/Port is interfaced on one/more of SoC internal buses. Buses carry data between various peripherals and Core inside SoC. In TM4C123GXL Launchpad Port A-F are interfaced on APB bus while Ports K-N and P-Q are available on the AHB bus – see Figure 1-1 in Datasheet .
APB is Advanced Peripheral Bus while AHB is Advanced High Speed Bus. AHB has high throughput and performance as compared to APB which is the legacy version of AHB bus architecture.
The first step is to select bus for the desired Port (Port-F in our case). A port bus can be selected via GPIO High-Performance Bus Control (GPIOHBCTL) Register-Figure-3.
- 0: APB bus selected
- 1: AHB bus selected
As we mentioned earlier only Ports K-N and P-Q are available on the AHB bus so we have no choice for Port F other than APB bus. So Let’s selected APB bus for Port F.
GPIOHBCTL_REG EQU 0x400FE06C ; use APB bus for GPIOF LDR R1, =GPIOHBCTL_REG LDR R0, [R1] AND R0, R0, #0x1F ; clear bit-5 STR R0, [R1]
2. GPIOx Clock:
To reduce power consumption, by default various SoC modules (GPIO, USART, UART etc.) and associated registers are disabled. In order to use them, clock must be enabled to them. On TM4C123GH6PM clock to various GPIOs can enabled/disabled via Run Mode Clock Gating Control Register 2 (RCGC2) – Figure-4.
As can be seen from Figure-2, the clock to GPIO Port-F is enabled/disabled via bit-5 (GPIOD-EN). Let’s enable Port-F module by setting bit-5 to 1.
RCGC2GPIO_REG EQU 0x400FE108 ; enable clock to GPIO-F LDR R1, =RCGC2GPIO_REG LDR R0, [R1] ORR R0, R0, #0x20 STR R0, [R1]
3. GPIOx Pin Direction:
Any GPIO pin can be configured as a Digital input or output. Before a GPIO pin is used, its direction needs to be configured appropriately. In our case as we want to blink LED, the GPIO pin needs to be configured as output. GPIO pins direction can be selected via GPIO Direction (GPIODIR) Register – Figure-5.
- 0: Corresponding pin is an input.
- 1: Corresponding pin is an output.
In our case as we want to blink LED, the GPIO pin (PF.1) needs to be configured as output by setting bit-1 to 1.
GPIOFDIR_APB_REG EQU 0x40025400 ; set PF.1 direction as output LDR R1, =GPIOFDIR_APB_REG MOV R0, #0x02 ; set bit-1 STR R0, [R1]
4. Unlock GPIOx Pin:
There are quite large number of peripherals available on compact size TM4C123GH6PM. Almost all of there peripherals have the capability to interact with outside world using I/O. Due to the compact size, not every peripheral can be assigned a dedicated physical pin on SoC due to size constrains. To accommodate these peripherals on SoC, various peripherals are multiplexed on a single I/O pin. At a time a pin be configured to be used dedicatedly for a specific peripheral.
For example PA.0,PA.1 pins can be configured to be used as Digital I/O or UART0 Tx, Rx respectively as an alternate function. In order to Lock a pin for specific purpose/function, TM4C123GH6PM implements software based hardware lock mechanism via GPIO Lock (GPIOLOCK) Register – Figure-6.
The GPIOLOCK register enables write access to the GPIO Commit (GPIOCR) Register register (discussed later). Writing 0x4C4F434B to the GPIO Lock (GPIOLOCK) register unlocks the GPIO Commit (GPIOCR) Register register. Writing any other value to the GPIOLOCK register re-enables the locked state.
Let’s unlock GPIO Commit (GPIOCR) Register.
; gpio registers GPIOFLOCK_APB_REG EQU 0x40025520 ; register values GPIO_UNLOCK_VAL EQU 0x4C4F434B ; unlock GPIOCR Register for write access LDR R1, =GPIOFLOCK_APB_REG LDR R0, =GPIO_UNLOCK_VAL STR R0, [R1]
5. GPIOx Pin Functionality Unlock:
Once GPIO Commit (GPIOCR) Register – Figure-7, is unlocked. Its time to define:
1. Pins State (Pull-UP/Down),
2. Digital Functionalities (Digital I/O or Alternate function).
The GPIO Commit (GPIOCR) Register enables various registers (PIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN register) to configure a pin for above specifications. The GPIO Commit (GPIOCR) Register can only be written when its unlocked via GPIO Lock (GPIOLOCK) – previous step.
- 0: The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits cannot be written for respective pin.
- 1: The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits can be written for respective pin.
Let’s enable GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN for PF.1 (LED Pin) – Figure-2.
; gpio registers GPIOFCR_APB_REG EQU 0x40025524 ; unlock GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN for PF.1 LDR R1, =GPIOFCR_APB_REG LDR R0, [R1] ORR R0, R0, #0x02 STR R0, [R1]
6. GPIOx Pin state:
The GPIO pin can be internally pulled-up or pulled-down thus setting the default Pin state to HIGH or LOW respectively. When pulled-high, the GPIO pin will remain in HIGH state until it is pulled down by software and vise versa.
Pull-up/down states are needed in situations where a pins needs remain in some state before a transition to be detected as an event e.g. UART start/stop bits. Though in this tutorial this step is optional; in the next tutorial the concept will become more clear.
The GPIO pin pull-up/down state can be selected via GPIO Pull-Up Select (GPIOPUR) and GPIO Pull-Down Select (GPIOPDR) respectively registers – Figure-8,9.
Note: Setting a bit in the GPIOPUR register automatically clears the corresponding bit in the GPIOPDR register.
Let’s set pull-up GPIO PF.1 pin high (LED ON) initially. Pull-Up is not mandatory.
GPIOPURF_APB_REG EQU 0x40025510 ; pull up PF.1 LDR R1, =GPIOPURF_APB_REG LDR R0, [R1] ORR R0, R0, #0x02 STR R0, [R1]
7. GPIOx Pin Digital Enable:
By default digital function is disabled for GPIOx Pins. They do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin as a digital input or output (either GPIO or alternate function), the corresponding GPIO Digital Enable (GPIODEN) – Figure-10, bit must be set.
- 0: The digital functions for the corresponding pin are disabled.
- 1: The digital functions for the corresponding pin are enabled.
Let’s enable Digital functionality for PF.1.
; gpio registers GPIOFDEN_APB_REG EQU 0x4002551C ; enable digital functionality for PF.1 LDR R1, =GPIOFDEN_APB_REG MOV R0, #0x02 STR R0, [R1]
8. Digital Write:
By now we configured everything we need. The last step is to write 0,1 i.e (Pin Low, High) to desired configured output pin. 0,1 can be writen to digital pins via GPIO Data (GPIODATA) register – Figure-11.
- 0: The digital is set Low.
- 1: The digital is set High.
NOTE: The GPIODATA has only one address but this register is virtually mapped to 256 locations in the address space i.e. GPIODATA + 0, GPIODATA+0x1, …. GPIODATA+0xFF. Each location is capable of setting Digital data to single pin depending on GPIODATA[9:2] address bits. The address bits 2-9 are associated with Digital pins 0-7 – Figure-12.
During a write, if the address bit associated with that data bit is set, the value of the GPIODATA register is altered. If the address bit is cleared, the data bit is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in Figure 12, where u indicates that data is unchanged by the write. This example demonstrates how GPIODATA bits 5, 2, and 1 are written.
For GPIOF, the GPIODATA base address (for APB bus) is: 0x40025000. As we need to write to PF.1 pin which from Figure-12 corresponds to bit-3. so bit-3 needs to be set in order for write operation to be effective. so the address of GPIODATA register for GPIOF Pin-1 will be 0x40025008 (bit-3 set).
; gpio registers GPIOFDATA_APB_REG EQU 0x40025008
Finally we reached a point where actual blinky operation can be implemented. As per tutorial requirements, RED LED (PF.1) needs to be toggle after some delay. The functionality is achieved via the following code snippet.
; register values DELAY_VAL EQU 500000 LDR R1, =GPIOFDATA_APB_REG loop LDR R2, =DELAY_VALUE ; dummy delay delay SUB R2, R2, #0x1 CMP R2, #0 BNE delay ; toggle PF.1 pin LDR R0, [R1] EOR R0, R0, #0x02 STR R0, [R1] B loop
For complete source code refer to the Github links given at the start of this tutorial.