Introduction to ARM CMSIS

Keywords: Embedded systems, ARM, CMSIS


The Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor that provides a standardized interface for the upper layer software to interact with processor core and other peripherals.

On low level, CMSIS is toolchain and vendor-independent set of Optimized ‘C’ MACROS and functions that hides the core differences across the Cortex families to enhance portability. The statement will be more clear once the idea of SoC becomes more clear.

1. The Concept of SoC

As this tutorial is about ARM CMSIS, let me ask you a very simple question:

ARM Cortex-M is a Microcontroller (MCU) or a Microprocessor?

Well if you think its a Microcontroller, You are Wrong!!! As a matter of fact ARM itself is a Processor Core designed for deeply embedded Low Power Applications. The Processor Core is used by many silicon vendors and add their own memory and peripherals to build a Complete System on Chip (SoC) or Simply MCU.

As an example Figure-1 shows the STM32F429-Discovery board which contains STM32F429ZI MCU. Magnifying the big picture reveals that the whole system consists of the following major parts.

  1. ARM Cortex-M4 → Provided by ARM
  2. Memory and Peripherals → Provided by ARM
  3. On board LCDs and other ICs → Provided by third Party

Collectively the first two are called SoC.

Figure-1: Inner view of STM32f429-Discovery

There are more than 15 silicon vendors who extend the same idea and use their own peripherals around Cortex-M processors to build their own versions of MCUs for Market Applications.

2. ARM CMSIS

Now that we have better understanding of what SoC is, Let’s discuss ARM CMSIS.

From above discussion one thing is clear that all these SoC share one thing – The Core i.e. Cortex-M Processor! This means that a software written to work with Core Only (not peripherals) should run on all SoCs independent of vendors!

Keeping in mind the same concept, ARM developed; a toolchain and vendors independent set of MACROS and Functions to be used as an abstact layer for accessing the underlying Processor Core services like Systick, NVIC etc. etc.

The ARM CMSIS is expanded by silicon vendors to provide standardized access to their own peripherals apart from the processor core. This leads to two layer CMSIS structure i.e. Core Peripheral Access Layer and Device Peripheral Access Layer. The first one is vendor independent while the later on is vendor dependent.

2.1 Core Peripheral Access Layer: contains name definitions, address definitions and helper functions to access core registers and peripherals. It also defines a device independent interface for RTOS Kernels that includes debug channel definitions.
2.2 Device Peripheral Access Layer: Provides address definitions for all device peripherals. This is provided by the silicon vendors e.g. ST, NXP, TI etc.
2.3 Access Functions for Peripherals (optional): Any additional helper functions for peripherals. This is also provided by the silicon vendors.

Figure-2 shows these vendor-independent and dependent layers.

Figure-2: CMSIS vendor independent and dependent layers

Now that we understood the basics of CMSIS its worth mentioning that CMSIS hides the ARM Core differences only. For example it provides portable layer and hides details if you want to migrate from Cortex-M0 to Cortex-M4. BUT as mentioned in SoC introductory section, each vendor adds his own set of peripherals to ARM Core. So the device dependent part of CMSIS will not be portable across different vendors – may it is for the same vendor like migrating from STM32f407VG to STM32F429ZI but certainly not in case of cross vendors MCUs e.g. Applications written for STM32f407VG using CMSIS may not run on TI TM4c123GH6PM though both uses the same ARM Cortex-M4 core for their SoC.

When migrating between two Cortex devices with the same core, but from different silicon vendors, CMSIS won’t help any as all the processor core peripherals are identical, any proprietary solution would work in the same way. However the non-core, not standardized peripherals can be (mostly they are) wildly different [2].

3. CMSIS Components

Since the birth of CMSIS; it has expanded significantly covering wide span of functionalities. The following figure shows various CMSIS Components. We will not go into detials of each component as this is just an introductory tutorial.

Figure-3: Cortex Microcontrollers Software Interface Standard (CMSIS)

CMSIS-Core: The CMSIS-Core consists bare-metal registers definitions and other relevant MACROS for accessing various on core and on chip peripherals.

CMSIS-RTOS: Common API for Real-Time Operating Systems along with reference implementation based on RTX. It provides a standardized programming interface that is portable to many RTOS and enables software components that can work across multiple RTOS systems.

CMSIS-DSP: CMSIS-DSP library is a rich collection of DSP functions that Arm has optimized for the various Cortex-M processor cores. CMSIS-DSP is widely used in the industry and enables also optimized C code generation from various third-party tools.

CMSIS-DAP: CMSIS-DAP Debug Access Port. Standardized firmware for a Debug Unit that connects to the CoreSight Debug Access Port. CMSIS-DAP is distributed as a separate package and is well suited for integration on evaluation boards. This component is provided as separate download.

CMSIS-SVD: CMSIS-SVD System View Description for Peripherals. Describes the peripherals of a device in an XML file and can be used to create peripheral awareness in debuggers or header files with peripheral register and interrupt definitions.

CMSIS-DSP: CMSIS-DSP DSP Library Collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). The library is available for all Cortex-M cores. Implementations that are optimized for the SIMD instruction set are available for Cortex-M4, Cortex-M7, and Cortex-M33.

CMSIS-NN: CMSIS-NN is a collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint of neural networks on Cortex-M processor cores.

References:

[1] – Cortex Microcontroller Software Interface Standard

[2] – Benifits of Cortex Microcontroller Software Interface Standard



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