ARM Cortex-M3/M4 – Boot Sequence

Keywords: Embedded systems, ARM, Boot Sequence


The boot up Process of Embedded SoCs is a multi-step sequence where the on-chip system passes through several complex states before reaching user application code. The boot sequence of Embedded Micrcontrollers/SoCs is quite different from boot sequence of Desktop PCs. There are many Embedded SoCs architectures out there in the market. It is practically impossible to discuss each architecture in detail here. In this article we will deep dive in Embedded Microcontrollers boot up process in general and ARM Cortex-M in particular.

The whole boot up process is defined by both the underlying Hardware State Machine and Low level Software defined behavior. The Hardware mainly consists of CPU/Processor Core and Internal SoC Peripheral Units that controls what happens from the point the power is applied to SoC to the point where the Processor jumps to Reset Vector in Vector Table (Explained shortly). This is fixed for each architecture. On the other hand the low level Software defines what happens after jump to Reset Vector and before calling user defined main() function – Figure-1.

Figure-1: Inner view of STM32f429-Discovery

1. SoC Hardware, The big Picture

From very high level, the Embedded SoC chips only contain CPU Core/Processor Unit. The chip itself contains many additional hardware Digital Logic Units like GPIO, UART, EDMA that assists CPU with various on-chip functionalities and communicating with off-chip and outside world – Figure-2.

Figure-2: System on Chip (STM32f429-Discovery)

Apart from these on-chip peripherals there are additional Digital Logic Units that actually controls Hardware Level System functionalities/behavior. Let’s call this hardware Logic the FSM-Logic (Finite State Machine Logic) just for illustration purpose as shown in below figure.

Figure-3: System on Chip with FSM-Logic

1.1 FSM-Logic Tasks

  • Keep the CPU Unit in Reset state until it perform hardware defined actions.
  • Sample/Read Endianness (Big-endian, little-endian) Pin if available. This is very important as all further instructions/data is interpreted accordingly.
  • Sample/Read boot pins (if any). Modern Processor can boot from many source like internal/external RAM/ROM/Flash, Serial, and Network etc. These pins input defines the boot source and Location (in memory map).
  • Reset SoC internal Peripherals (UART, internal SRAM, I2C etc.)
  • Initialize CPU Core/Control Registers and other peripheral Registers to their default values.

1.2 Initial Hardware Level Bootstrapping

Initial Hardware Level Bootstrapping refers any memory transfer or system setup that is performed by on-chip Hardware before the CPU Core Unit Reset is released. FSM-Logic tasks mentioned above come under the category of initial bootstrapping. This is highly architecture dependent and may be optional in some cases. In this step of boot process:

  • Memory Contents MAY be transferred from some memory locations to internal Registers. e.g. In ARM Cortex-M profile Cores, apart from setting various registers to their default values, the contents from Memory Location 0x00000000 is copied to Stack Pointer Register (R13) and contents from Memory location 0x00000004 is copied to Program Counter (R15). At this point there are no copy instruction, yet this is performed by Internal Hardware.
  • Memory to Memory transfer i.e. like from internal/external ROM to internal/external RAM for faster execution. One example of such bootstrapping is TMS320C6713 Digital Signal Processor. TMS320C6713 internal EMIF on boot (while CPU is kept in RESET state) copies 1K byte of code from boot source (external ROM/Flash) to internal RAM (iRAM). This copy operation is performed by EMIF logic Unit while the CPU core remains in Reset State.
  • It may Copy Vector Table to RAM to reduce Interrupt Latency.

Till this point, the Registers have been set to their default values, internal Logic Units have been Reset, initial bootstrapping is done, all the settings that the CPU might expect have been done. NOW its time to transfer control to CPU so that the boot process is further proceeded by CPU itself. So the CPU Reset pin is released and control is handover to CPU.

2. Vector Table

Each Processor Architecture has pre-defined (default) Memory Locations where it jumps (execution instructions from that location forward) when associative event/Exception/Interrupt occurs i.e. Some memory locations or group of locations are reserved for each predefined event/Exception/Interrupt. These memory locations group are consecutive most of the time. These pre-defined Memory Locations are collectively called Vector table i.e. A table of memory locations to which different CPU-Event (Interrupts/Exceptions) vectors points. (Remember high school physics – vectors have direction, the concept is similar here).

The format of vector table is unique to the underlying architecture. For example in case of ARMv5 and later the Vector table consists of single 32-bit memory location per Exception/Interrupt. Other architecture like may have reserved certain number of memory location for each Exception/Interrupt. In the former case only the address of Exception/Interrupt Handler (function to handle the Exception/Interrupt) is placed with is copied automatically to Program Counter upon Exception/Interrupt. In the later case, Processor jumps to the Exception/Interrupt location and start executing the instructions from that location. No Address is copied to Program Counter. The example of later is TMS320C6713 DSP processor in which 8 words consecutive memory locations are reserved for each Exception/Interrupt. The user has to either to adjust the ISR within these locations are jump (via JUMP Instruction) to the ISR at other location.

This Vector table has pre-defined fixed locations for each architecture defined Interrupt/Event. If the vector table is relocated (if allowed) the CPU must be informed. The following figure shows ARM Cortex-M Vector table starting from 0x00000000 memory address.

Figure-4: ARM Cortex-M Vector Table

As an Example, when CPU Reset pin is released, this Event is called Reset Interrupt. i.e. Reset itself is a non maskable interrupt to CPU. Reset Vector is the entry in Vector table from where Processor starts execution immediately after system Reset – in other words Processor jumps to Reset Vector Memory Location once powered up. On case of ARM Cortex-M processors, the Reset Vector is located at memory location 0x00000004 by default. The content of this location are copied to PC (R15).

Once the CPU reaches to the Reset Exception/Interrupt; CPU is now ready to start executing instruction. This is the point where System hardware has completely boot up and system is ready to go through software defined actions.

3. Software Define Actions:

From Reset Exception/Interrupt onward till application code (In C, main () function) is totally User/Compiler/Development Environment Toolchain dependent. If you are actually coding from scratch right from Reset Vector (usually in Assembly) then the system is practically fully under your control. Large applications are often coded in higher level language like C as Assembly Code is hard to maintain in high scale applications.

Note: main () → is a C language Program entry point and requires C-environment to be ready i.e. Stack/Heap sections should be properly initialized, various segments (.data, .bss etc.) should be properly copied to RAM. So it means there need to be some code that should perform these initialization tasks and environment setup before main function is called. Here is what “Startup Code” comes into action. Think of this Startup Code as CRT0.o linked into C Programs that performs any initialization work before the main () function is called.

The code is usually organized as bellow.

Figure-5: Startup Code Integration with Application code

The Startup code is basically the one that actually does software level Initialization (stack/heap/data segments etc.) and after doing the necessary initialization calls the main() – Figure-6. Usually at Reset Vector, there is either a jump instruction to the entry point of this startup code or either the address of entry point is placed at Reset Vector.

Figure-6: Execution from Reset Vector to main()

The startup code is usually provided by the toolchain vendors. Followings are entry points of few vendors startup codes.

In ARM Cortex-M:

Reset_Handler –> __main –> __rt_entry –> __user_setup_stackheap() –> __rt_stackheap_init() …..–> main()

Note: __main is the entry point to ARM C-Library not the application code entry point.

In TI-C6000:

Reset_Vector –> _c_int00 –> (_TI_STACK_SIZE,__TI_STATIC_BASE, __TI_STACK_END)…. –> main()

Note: _c_int00 is the entry point to TI startup Routine.

4. Secondary Stage Bootloader:

Secondary stage bootloader is usually required in systems where you want your code or System needs your code (.text segment) to be in RAM and hardware initial bootstrap either only copies a certain amount of code in RAM or either does only the Hardware Registers initialization. In either case you need your whole/remaining code to be copied to RAM before the main () function is called. In that case you need to manually write code that actually copies the code into RAM memory.

Remember, this 2nd level bootloader code should be in the portion which is copied by 1st stage hardware bootstrapping. This is because System (under consideration) needs code to be in RAM memory for execution and if the 2nd stage bootloader is not in RAM memory, or not fully copied then it will not be able to load remaining application code into RAM.

Bootloader code is usually written in assembly. This is because it is one of the first piece of codes that are executed by the processor as a part of boot up process. At that point no stack or C-environment is ready to handle code written in high level language.

As an example, Texas Instruments TMS320C6713 Processor copies first 1Kbytes of memory into internal RAM as a part of hardware bootstrap process. If your code exceeds 1K bytes (which is usually the case) then you have to write a secondary bootloader code to copy remaining code into internal RAM memory.

NOTE: This is the case where your system requires the execution code (.text) to be in RAM. Some systems are fine with executing instructions from memory mapped non-volatile memories like NOR flash, EEPROM etc. This is called XIP (Execution in Place). In that case code is directly executed from Memory mapped permanent memory while the remaining sections/segments like .data, .bss are copied by startup code. In such scenarios you don’t need or worry about secondary bootloader.

In Simple Words:

If your system need secondary bootloader, the Software boot sequence becomes:

Reset_Handler –> startup Code –> Secondary Bootloader –> main ()

If your system doesn’t need secondary bootloader, the Software boot sequence becomes:

Reset_Handler –> startup Code –> main ()

By now ULTIMATELY the user defined main () function is called. From now onward what happens is purely user defined. The boot up process completes at this point.

Summary (Generalized):

  1. Power is applied to SoC, the internal SoC hardware (FSM-Logic) Resets internal Hardware Units, Set internal Registers to their default values.
  2. The CPU jumps to Reset Vector.
  3. At Reset Vector there is usually a jump instruction to Reset Handler (function that is called after Reset).
  4. The Reset Handler transfer control to startup code.
  5. The startup code, after doing the necessary initialization, transfer control to secondary stage bootloader (if required).
  6. The secondary stage bootloader, after loading the code into RAM memory, transfer control to user defined main () function.
  7. If secondary stage bootloader is not required, the startup code transfer control directly to user defined main () function.
  8. Now onward further control is based on user define code in main () function.

Summary (ARM Cortex-M):

  1. Power is applied to SoC, the internal SoC hardware (FSM-Logic) Resets internal Hardware Units, Set internal Registers to their default values.
  2. The Contents of Memory location 0x00000000 is copied to Main Stack Pointer – MSP (R13).
  3. The Contents of Memory Location 0x00000004 is copied to Program Counter – PC (R15). At memory location 0x00000004 the address of Reset Handler is placed by the programmer.
  4. The Reset Handler transfer control to startup code.
  5. The startup code, after doing the necessary initialization, call the user application main() function.
  6. Now onward further control is based on user define code in main () function.

References:

[1] – ARM Cortex-M Info Center



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