Introduction to I2C Protocol
I2C (Inter Integrated Circuit) is a two wire Synchronous half-duplex communication bus specifications used to interface low data rate devices. I2C was originally developed by Philips Semiconductor in 1982. is a multi-master, multi-slave, serial communication bus interface. I2C is well suited for for peripherals where simplicity and low manufacturing cost are more important than speed .
In contrast to SPI, I2C is address based communication where a device is selected via its alloted address instead of physical selection connection like SS (Slave Select) in SPI. I2C follows Master-Slave architecture where master has full control over the overall bus communication. Unlike SPI where specification doesn’t mention any data rates / speed limitations ( maximum half of frequency), I2C specifications do define upper limits on maximum data rates that can be achieved while meeting specific I2C specification version.
Compared to other bus communication specifications/standards like SPI/UART, I2C is relatively complex yet I2C combines the advantages of both UART and SPI. like SPI, I2C is also intended to be used for short range communication merely on board devices. While SPI doesn’t specify Multi-Master bus interface to slave, the I2C does provide the facility of adding more Masters on bus to exchange data with slaves. Similarly like UART, I2C uses just two wires to data exchanges with the exception that I2C is half-duplex while UART is full-duplex.
One of the major advantages of I2C is that the I2C specifications are more like Connection Oriented protocol i.e. Acknowledge from slave is required (if specified) on successful reception of data. While SPI and UART serial communication don’t specify any such data acknowledgment from Salve/Receiver.
1. I2C Signals:
On hardware level, I2C bus consists of just two wires to exchange data i.e. SCL, SDA. The following Figure shows the simplest case of I2C bus interface between a single Master and Single slave.
The I2C bus lines i.e. SCL and SDA follows open-drain technology. The bus lines remain in high impedance state i.e. they can neither be driven high (Logic-1) or drive low (Logic-0). The I2C hardware (peripheral module) can only pull down both line to logic-0 (bit-0)when required and can’t set them to logic-1 (send bit-1). In order to cope with this situation, these lines are pulled up by external appropriate resistors (Figure-2) which keep the bus lines at logic-1. The I2C hardware pulls the SDA line when bit-0 is to be send and release the SDA line (the pull-up resistor automatically pulls the line high) whenever bit-1 is required to be send. The same thing happens with SCL line clock cycles.
The value of Pull-up resistor (Rp) depends on line voltage, current, capacitance and speed of communication.
2. I2C Frame/Packet:
In I2C protocol, data is synchronously and serially transfered on I2C bus. The serial data is chunked in the form of frames/packets with minimum length of 11-bits. The I2C data frame consists of the following fields, Figure-3.
- Start bit (1-bit)
- Address bits (7-bits / 10-bits)
- Read/Write bit (1-bit)
- ACK/NACK Acknowledgment bit (1-bit)
- Optional data byte (8-bits) + ACK/NACK bit
- Stop bit (1-bit)
2.1. Start bit/ Start Condition:
No transition on SDA line is allowed when SCL line is high (High Clock Cycle) except for start/stop conditions. When The SDA line switches from Logic-1 (high voltage) to a Logic-0 (low voltage) before the SCL line switches from high to low, the condition is considered as Start bit or Start of communication, Figure-4.
2.2. Slave Address:
As mentioned earlier, I2C bus specifications uses device address to uniquely identify a device on bus. I2C address uses 7-bits or 10-bits (depends on I2C version) unique address to each slave that identifies the slave when the master wants to talk to it.
7-bits Addressing: When using 7-bits addressing scheme, maximum number of 128 devices (7^2 = 128 addresses) can be connected on I2C bus. However some addresses are reserved for special purposes. Thus, only 112 addresses are available with the 7 bit address scheme. In 7-bits addressing scheme, the address is sent in first byte right after the start bit condition as shown in Figure-5.
Followings are reserved addresses .
- 0000 xxx
- 1111 xxx
Table-1 shows reserved addresses in 7-bits addressing scheme.
10-bits Addressing: In order to extend the limited range of devices that can be interfaced on I2C bus, a new 10-bits addressing scheme was introduced. Usually the hardware is backward compatible i.e. I2C supporting 10-bits addresses can also use 7-bits addressing scheme though forward compatibility is not guaranteed.
In order to send 10-bits address, the 10-addressing code (Table-1- Address Index: 8) is sent along with the most two most significant bits (MSB-9,8) of slave address in the first byte right after the start condition, Figure-6. Receiving the 10-bits addressing code (11110xx) causes the slave to switch to 10-bits addressing. If the salve accept the address, it sends an acknowledge (discussed later). Upon receiving acknowledgment bit, the master sends the remaining 8-bits of address as shown in Figure-6.
2.3. Read/ Write Bit:
The LSB (least significant bit) of first byte right after the start condition indicate whether the master wants read from Slave or write to Slave. If the master wants to send data to the slave, the read/write bit is a set to low (0). Similarly if the master is requesting data from the slave, it sets the bit to high (1).
2.4. Acknowledge/No-Acknowledge bit:
As mentioned earlier, I2C is sort of connection oriented bus protocol i.e. a configurable acknowledgment is sent from receiving device to confirm to the sender that the data has been received. In I2C frame, 1-bit is reserved for Acknowledge or No-Acknowledge receiver/slave response. When the slave accepts address/data byte, it sends Acknowledge (ACK) bit in response otherwise it sends back a No-Acknowledge bit (NACK).
If the address/data is accepted, the slave returns an ACK bit by pulling the SDA line low for one bit. On the other hand if the sent address/data is not accepted, the SDA line is left high for 1-bit which is considered as NACK on master side.
2.5. Stop bit/ Stop Condition:
When The SDA line switches from Logic-0 (high voltage) to a Logic-1 (low voltage) before the SCL line switches from high to low, the condition is considered as Stop bit or Stop of communication, Figure-7.
3. How I2C Works?
So far we have we have discussed the basics of I2C bus internals. Let’s discuss briefly how master communicate with slave nodes on I2C bus. Following are the steps.
- The master nodes sends start condition (Figure-4) to each connected slave nodes on I2C bus. This makes the slave nodes active for further bus transaction and start listening for the address.
- Next, the master device broadcasts slave address (7-bits/10-bits) along with Read/Write bit. This is the only data bytes’ to which all the slave devices on the bus listens.
- All the slave nodes compare their own address with the Master node sent address, if there is a match, the slave node sends back ACK bit by pulling the SDA line low for one clock cycle. Other slave nodes simply ignore further bus activity.
- The master exchange (read/write) data frames with the selected slave.
- After each data frame, the receiver node returns an ACK bit as an acknowledge of successful data frame reception.
- Once the transaction completes, the master node sends a stop condition (Figure-7) to the slave node as an indication of data transfer completion.
The overall transaction cycle is summarized in the following figure.
4. I2C Modes / Revisions:
I2C bus communication specifications has evolved significantly since 1982-the first release. Following table summarizes I2C major releases.
|1982||–||Standard Mode (Sm)||100khz|
|1992||Version 1||Fast Mode (Fm)||400khz|
|1988||Version 2||High Speed Mode (Hm)||2.3Mhz|
|2007||Version 3||Fast Mode Plus (Fm+)||–|
|2012||Version 4||Ultra Fast Mode (UFm)||5Mhz|
 – I2C Wikipedia