Introduction to SPI Communication
The Serial Peripheral Interface (SPI) is four wire Synchronous Serial Communication interface specification (Not Standard) used for short distance inter-peripheral communication in Embedded Systems. SPI was originally developed by Motorola in the mid 1980s . SPI is commonly used for short distance communication between Microcontroller and devjces like Memory (e.g. EEPROM, SdCards) , Sensors, LCDs etc. Typical Characteristics include:
- Master Slave Architecture
- Full-Duplex / half-Duplex (Implementation dependent)
- Higher Throughput compared to I2C and RS-232
- Flexible Data Rates
- Simple Hardware Interface
- Comparatively Low Power Consumption
- No Complex Addressing scheme for Slave selection
There are few downsides of SPI communication. For example SPI doesn’t support any hardware flow control. Similarly there is no data acknowledge support provided in SPI interface. SPI master has absolute no knowledge of whether the data has been received correctly or not. It doesn’t even know if there is a slave device listening to or ready for to receive data.
The beauty of SPI Protocol is that its specification doesn’t put any restriction on data rates. It totally depends on the driving hardware capabilities. The maximum data rates that can be achieved with SPI protocol is half of the highest supported frequency of underlying driving hardware.
● SCLK: Serial Clock generated by SPI Master
● MOSI: Master Out Slave In
● MISO: Master In Slave Out
● SS: Slave Select (Optional in case of only single Slave)
The following figure shows a general SPI Master-Slave Signals Interface.
The simplest case is when there is only one master and one slave as shown in the following figure.
2. How SPI Interface Works?:
Let’s explain in simple words how exactly SPI communication happens. First whenever master has to send data to any slave, it pulls down (logic 0) the SS (slave select line) of that particular slave. This inform slave to get ready for data as master is about to send a packet of data. Next, master initiate clock signal on SCK line. On each clock cycle, SPI master puts 1-bit of data to be send on MOSI line and reads exactly 1-bit of data on MISO line i.e. if master sends 8-bits of data on MOSI line, it will receives exactly 8-bits of data on MISO line simultaneously. if the slave didn’t put any data in response, the master will read all 0’s or 1’s as the sate of MISO line will remain constant.
The following figure shows SPI clock and data on SCK, MOSI and MISO lines respectively .
Hang in there if you didn’t understand the SPI signals diagram, we are not finished yet. There are few terms need to be define before we fully understand SPI clock and data signals. Let’s define some clock parameters.
2.1. Clock Parameters:
2.1.1. Clock Polarity (CPOL): This parameter basically signify which Clock Level (Low, High) edges should be used for data transmission and Sampling (Capture or Reception). The other half cycle level will be considered idle. There are two possible clock formats. i.e.
- CPOL = 0: (Non-Inverted) In this state Logic-1 of clock cycle (positive half clock cycle) is considered as an effective half clock cycle for SPI communication. The other level (Logic-0) is considered as an idle state.
- CPOL = 1: (Inverted) In this state Logic-0 of clock cycle (negative half clock cycle) is considered for as an effective half clock cycle for SPI communication. The other level (Logic-1) is considered as an idle state.
- Leading Edge: The starting edge of effective half cycle (CPOL = 0 -> Rising Edge, CPOL = 1 -> Falling Edge).
- Trailing Edge: The Ending edge of effective half cycle (CPOL = 0 -> Falling Edge, CPOL = 1 -> Rising Edge).
2.1.2. Clock Phase (CPHASE): The CPHASE defines at which edge of CPOL the data bit has to be placed on MOSI line and at which edge the data bit will be sampled (read) on MISO line.
- CPHASE = 1: With CPHASE = 1, data bit on (MOSI,MISO) will be sampled (read) on Trailing Edge of CPOL cycle. Data toggle (transmission) occurs on Leading Edge.
- CPHASE = 0: With CPHASE = 0, data bit on (MOSI,MISO) will be sampled (read) on Leading Edge of CPOL cycle. Data toggle (transmission) occurs on Trailing Edge.
3. SPI Modes:
Based on CPOL and CPHASE values, there are 4 possible combinations called SPI Modes. The following table-1,2 summarize SPI modes.
|Mode-0||In this mode the positive half clock cycle i.e. the Logic-1 is used as an effective half cycle for communication. The data bit is sampled (read) at leading edge and placed (transmit) at trailing edge of the effective clock cycle – Figure-7.|
|Mode-1||In this mode the positive half clock cycle i.e. the Logic-1 is used as an effective half cycle for communication. The data bit is sampled (read) at trailing edge and placed (transmit) at leading edge of the effective clock cycle – Figure-7.|
|Mode-2||In this mode the negative half clock cycle i.e. the Logic-0 is used as an effective half cycle for communication. The data bit is sampled (read) at leading edge and placed (transmit) at trailing edge of the effective clock cycle – Figure-7.|
|Mode-3||In this mode the negative half clock cycle i.e. the Logic-0 is used as an effective half cycle for communication. The data bit is sampled (read) at trailing edge and placed (transmit) at leading edge of the effective clock cycle – Figure-7.|
Table-1: SPI Modes
Table-2: SPI Modes – CPOL, CPHASE Combination
The following figures shows SPI modes in Signal Phase and Polarity form.
Now lets look back at Figure-3 and determine in which modes the devices are communicating over SPI bus. Let’s start from the left, as can be seen from the MOSI line, the line is high i.e. 1s’ are transmitted but we can’t determine on which edge it is transmitted?
On the transmission of third bit on MOSI line, as can be seen, the bit toggle (from 1 to 0) occurs at edge. This edge can be positive half clock cycle trailing edge or consecutive negative half clock cycle leading edge. So the clue is not clear yet. Let’s move ahead. As can be seen from the 5th data bit (bit-4), the data bits are changing (transmission) at leading edges of negative half clock cycles and read/sampled at trailing edge of the negative half clock cycle (the green line). In between the two edges the negative half clock cycle (Logic-0) is encapsulated. Which means CPOL = 1. Now as the data is placed on the leading edge of the negative half clock cycle (Logic-0) and sampled (read) at trailing edge of negative half clock cycle (Logic-0) so the CPHASE = 1. So from Table-2, the devices in Figure-3 are communicating in Mode-3 over SPI bus.